NEXPERIA 74HC595D is an 8-bit serial-in, serial or parallel-out shift register with output latches: 3-state. The shift and storage registers each have their own clocks. This device has a serial input (DS), a serial output (Q7S), and an asynchronous reset MR input. A LOW on MR will cause the shift register to be reset. On the SHCP input's LOW-to-HIGH transitions, data is shifted. On a LOW-to-HIGH transition of the STCP input, the data in the shift register is transferred to the storage register. When both clocks are linked, the shift register is always one clock pulse ahead of the storage register. When the output enable input (OE) is LOW, data from the storage register is output. When OE is set to HIGH, the outputs enter a high-impedance OFF state. The OE input's operation has no effect on the state of the registers.

Datasheet

Features

• Wide supply voltage range from 2V to 6V
• CMOS low power dissipation
• High noise immunity
• 8-bit serial input
• 8-bit serial and parallel output
• Storage register with 3-state output
• Shift register with direct clear
• Input CMOS level
• ESD protection

SPECIFICATIONS