Trimming at the wafer stage results in a very low input offset voltage (75 V maximum for OP07E). These low offset voltages obviate the requirement for external nulling in most cases. The OP07 also has a low input bias current (for the OP07E, 4 nA) and a high open-loop gain (200 V/mV). The OP07's low offset and strong open-loop gain make it ideal for high gain instrumentation applications. The non inverting circuit layout benefits from a wide input voltage range of 13 V minimum, a high CMRR of 106 dB (OP07E), and a high input impedance. Even at large closed-loop gains, excellent linearity and gain accuracy may be maintained. Offset and acquire stability with time or variation.

Features:

• Ultrastable vs. time: 1.5 µV/month (max.)
• Low noise: 0.6 µV p-p (max.)
• Wide input voltage range: ±14 V
• Wide supply voltage range: ±3 V to ±18 V
• Fits 725, 108A/308A, 741, and AD510 sockets
• 125°C temperature-tested dice